Conference
20 | “A 4Gb LPDDR2 STT-MRAM with compact 9F2 1T1MTJ cell and hierarchical bitline architecture” | |
| Kwangmyoung Rho, Kenji Tsuchida, Dongkeun Kim, Yutaka Shirai, Jihyae Bae, Tsuneo Inaba, Hiromi Noro, Hyunin Moon, Sung-Woong Chung, Kazumasa Sunouchi, Jinwon Park, Kiseon Park, Akihito Yamamoto, Seoungju Chung, Hyeongon Kim, Hisato Oyamatsu, Jonghoon Oh IEEE International Solid- State Circuits Conference - (ISSCC), 2017 | ||
19 | “4Gb perpendicular STT-MRAM with compact cell structure and beyond” | |
| T. Kishi, M. Yoshikawa, T. Nagase, Hirokazu Aikawa, Sung-Woong Chung, J. Park, H. Kanaya, , K. Park, G. Kim, M. Lee, K. Sunouchi, A. Yamamoto, K. Rho, K. Tsuchida, ,J. Yi, ,H. Kim, Y. Chun, S. Hong, H. Oyamatsu 2017 IEEE International Magnetics Conference (INTERMAG), April 2017 | ||
| “A 4Gb LPDDR2 STT-MRAM with compact 9F2 1T1MTJ cell and hierarchical bitline architecture” | |
| Kwangmyoung Rho, Kenji Tsuchida, Dongkeun Kim, Yutaka Shirai, Jihyae Bae, Tsuneo Inaba, Hiromi Noro, Hyunin Moon, Sung-Woong Chung, Kazumasa Sunouchi, Jinwon Park, Kiseon Park, Akihito Yamamoto, Seoungju Chung, Hyeongon Kim, Hisato Oyamatsu, Jonghoon Oh IEEE International Solid- State Circuits Conference - (ISSCC), 2017 | |
20 | |
| “4Gb perpendicular STT-MRAM with compact cell structure and beyond” | |
| T. Kishi, M. Yoshikawa, T. Nagase, Hirokazu Aikawa, Sung-Woong Chung, J. Park, H. Kanaya, , K. Park, G. Kim, M. Lee, K. Sunouchi, A. Yamamoto, K. Rho, K. Tsuchida, ,J. Yi, ,H. Kim, Y. Chun, S. Hong, H. Oyamatsu 2017 IEEE International Magnetics Conference (INTERMAG), April 2017 | |
19 | |
2016
18 | “4Gbit density STT-MRAM using perpendicular MTJ realized with compact cell structure” | |
| Sung-Woong Chung, SK Hynix, T. Kishi, J. W. Park, M. Yoshikawa, K. S. Park, T. Nagase, K. Sunouchi, H. Kanaya, G. C. Kim, K. Noma, M. S. Lee, A. Yamamoto, K. M. Rho, K. Tsuchida, S. J. Chung, J. Y. Yi, H. S. Kim, Y.S. Chun, H. Oyamatsu, S. J. Hong Proc. International Electron Devices Meeting (IEDM), 2016 | ||
| “4Gbit density STT-MRAM using perpendicular MTJ realized with compact cell structure” | |
| Sung-Woong Chung, SK Hynix, T. Kishi, J. W. Park, M. Yoshikawa, K. S. Park, T. Nagase, K. Sunouchi, H. Kanaya, G. C. Kim, K. Noma, M. S. Lee, A. Yamamoto, K. M. Rho, K. Tsuchida, S. J. Chung, J. Y. Yi, H. S. Kim, Y.S. Chun, H. Oyamatsu, S. J. Hong Proc. International Electron Devices Meeting (IEDM), 2016 | |
18 | |
2012
17 | “Integration of 4F2 selector-less crossbar array 2Mb ReRAM based on transition metal oxides for high density memory applications” | |
| Hyung Dong Lee, S. G. Kim, K. Cho, H. Hwang, H. Choi, J. Lee, S. H. Lee, H. J. Lee, J. Suh, S.-O. Chung, Y. S. Kim, K. S. Kim, W. S. Nam, J. T. Cheong, J. T. Kim, S. Chae, E.-R. Hwang, S. N. Park, Y. S. Sohn, C. G. Lee, H. S. Shin, K. J. Lee, K. Hong, H. G. Jeong, K. M. Rho, Y. K. Kim, S. Chung, J. Nickel, J. J. Yang, H. S. Cho, F. Perner, R. S. Williams, J. H. Lee, S. K. Park, S.-J. Hong Digest of Technical Papers - Symposium on VLSI Technology, 2012 | ||
| “Integration of 4F2 selector-less crossbar array 2Mb ReRAM based on transition metal oxides for high density memory applications” | |
| Hyung Dong Lee, S. G. Kim, K. Cho, H. Hwang, H. Choi, J. Lee, S. H. Lee, H. J. Lee, J. Suh, S.-O. Chung, Y. S. Kim, K. S. Kim, W. S. Nam, J. T. Cheong, J. T. Kim, S. Chae, E.-R. Hwang, S. N. Park, Y. S. Sohn, C. G. Lee, H. S. Shin, K. J. Lee, K. Hong, H. G. Jeong, K. M. Rho, Y. K. Kim, S. Chung, J. Nickel, J. J. Yang, H. S. Cho, F. Perner, R. S. Williams, J. H. Lee, S. K. Park, S.-J. Hong Digest of Technical Papers - Symposium on VLSI Technology, 2012 | |
17 | |
2011
16 | “Offset buried metal gate vertical floating body memory technology with excellent retention time for DRAM application” | |
| Sang-Min Hwang, S. Banna, C. Tang, S. Bhardwaj, M. Gupta, T. Thurgate, D. Kim, Jungtae Kwon, Joong-Sik Kim, Seung-Hwan Lee, J.-Y. Lee, S.-J. Chung, Jung W. Park, Sung-Woong Chung, Sang-Bock Cho, J.-S. Roh, Jiho Lee, Michael Van Buskirk, S.-J. Hong Digest of Technical Papers - Symposium on VLSI Technology, 2011 | ||
15 | “The Effect of Tunnel Barrier at Resistive Switching Device for Low Power Memory Applications” | |
| Hyejung Choi, Jaeyun Yi, Sangmin Hwang, Sangkeum Lee, Seokpyo Song, Seunghwan Lee, Jaeyeon Lee, Donghee Son, Jinwon Park, Suk-Ju Kim, Ja-Yong Kim, Sunghoon Lee, Jiwon Moon, Choidong Kim, Jungwoo Park, Moonsig Joo, JaeSung Roh, Sungki Park, Sung-Woong Chung, Junghoon Rhee, Sung Joo Hong 2011 3rd IEEE International Memory Workshop (IMW) | ||
| “Offset buried metal gate vertical floating body memory technology with excellent retention time for DRAM application” | |
| Sang-Min Hwang, S. Banna, C. Tang, S. Bhardwaj, M. Gupta, T. Thurgate, D. Kim, Jungtae Kwon, Joong-Sik Kim, Seung-Hwan Lee, J.-Y. Lee, S.-J. Chung, Jung W. Park, Sung-Woong Chung, Sang-Bock Cho, J.-S. Roh, Jiho Lee, Michael Van Buskirk, S.-J. Hong Digest of Technical Papers - Symposium on VLSI Technology, 2011 | |
16 | |
| “The Effect of Tunnel Barrier at Resistive Switching Device for Low Power Memory Applications” | |
| Hyejung Choi, Jaeyun Yi, Sangmin Hwang, Sangkeum Lee, Seokpyo Song, Seunghwan Lee, Jaeyeon Lee, Donghee Son, Jinwon Park, Suk-Ju Kim, Ja-Yong Kim, Sunghoon Lee, Jiwon Moon, Choidong Kim, Jungwoo Park, Moonsig Joo, JaeSung Roh, Sungki Park, Sung-Woong Chung, Junghoon Rhee, Sung Joo Hong 2011 3rd IEEE International Memory Workshop (IMW) | |
15 | |
2010
14 | “Highly reliable and fast nonvolatile hybrid switching ReRAM memory using thin Al2O3 demonstrated at 54nm memory array” | |
| Jaeyun Yi, Hyejung Choi, Seunghwan Lee, Jaeyeon Lee, Donghee Son, Sangkeum Lee, Sangmin Hwang, Seokpyo Song, Jinwon Park, Sookjoo Kim, Wangee Kim, Ja-Yong Kim, Sunghoon Lee, Jiwon Moon, Jinju You, Moonsig Joo, JaeSung Roh, Sungki Park, Sung-Woong Chung, Junghoon Lee, Sung-Joo Hong Digest of Technical Papers - Symposium on VLSI Technology, 2010 | ||
13 | “Fully integrated 54nm STT-RAM with the smallest bit cell dimension for high density memory application” | |
| Suock Chung, K.-M. Rho, Sung-Doo Kim, H.-J. Suh, Do Jin Kim, H.J. Kim, S.H. Lee, J.-H. Park, H.-M. Hwang, S.-M. Hwang, J.-Y. Lee, Y.-B. An, J.-U. Yi, Y.-H. Seo, D.-H. Jung, M.-S. Lee, Sang-Bock Cho, J.-N. Kim, G.-J. Park, Gyuan Jin, A. Driskill-Smith, Vladimir Nikitin, Adrian E Ong, X. Tang, Yongki Kim, J.-S. Rho, S.-K. Park, Sung-Woong Chung, J.-G. Jeong, S.J. Hong Proc. International Electron Devices Meeting (IEDM), 2010 | ||
12 | “Vertical Double Gate Z-RAM technology with remarkable low voltage operation for DRAM application” | |
| Joong-Sik Kim, Sung-Woong Chung, Tae-Su Jang, Seung-Hwan Lee, Dong-Hee Son, Seoung-Ju Chung, Sang-Min Hwang, Srinivasa Banna, Sunil Bhardwaj, Mayank Gupta, Jungtae Kwon, David Kim Digest of Technical Papers - Symposium on VLSI Technology, 2010 | ||
| “Highly reliable and fast nonvolatile hybrid switching ReRAM memory using thin Al2O3 demonstrated at 54nm memory array” | |
| Jaeyun Yi, Hyejung Choi, Seunghwan Lee, Jaeyeon Lee, Donghee Son, Sangkeum Lee, Sangmin Hwang, Seokpyo Song, Jinwon Park, Sookjoo Kim, Wangee Kim, Ja-Yong Kim, Sunghoon Lee, Jiwon Moon, Jinju You, Moonsig Joo, JaeSung Roh, Sungki Park, Sung-Woong Chung, Junghoon Lee, Sung-Joo Hong Digest of Technical Papers - Symposium on VLSI Technology, 2010 | |
14 | |
| “Fully integrated 54nm STT-RAM with the smallest bit cell dimension for high density memory application” | |
| Suock Chung, K.-M. Rho, Sung-Doo Kim, H.-J. Suh, Do Jin Kim, H.J. Kim, S.H. Lee, J.-H. Park, H.-M. Hwang, S.-M. Hwang, J.-Y. Lee, Y.-B. An, J.-U. Yi, Y.-H. Seo, D.-H. Jung, M.-S. Lee, Sang-Bock Cho, J.-N. Kim, G.-J. Park, Gyuan Jin, A. Driskill-Smith, Vladimir Nikitin, Adrian E Ong, X. Tang, Yongki Kim, J.-S. Rho, S.-K. Park, Sung-Woong Chung, J.-G. Jeong, S.J. Hong Proc. International Electron Devices Meeting (IEDM), 2010 | |
13 | |
| “Vertical Double Gate Z-RAM technology with remarkable low voltage operation for DRAM application” | |
| Joong-Sik Kim, Sung-Woong Chung, Tae-Su Jang, Seung-Hwan Lee, Dong-Hee Son, Seoung-Ju Chung, Sang-Min Hwang, Srinivasa Banna, Sunil Bhardwaj, Mayank Gupta, Jungtae Kwon, David Kim Digest of Technical Papers - Symposium on VLSI Technology, 2010 | |
12 | |
2009
11 | “Highly scalable Z-RAM with remarkably long data retention for DRAM application” | |
| Tae-Su Jang, Joong-Sik Kim, Sang-Min Hwang, Young-Hoon Oh, Kwang-Myung Rho, Seoung-Ju Chung, Su-Ock Chung, Jae-Geun Oh, S. Bhardwaj, Jungtae Kwon, D. Kim, M. Nagoga, Yong-Taik Kim, Seon-Yong Cha, Seung-Chan Moon, Sung-Woong Chung, Sung-Joo Hong, Sung-Wook Park Digest of Technical Papers - Symposium on VLSI Technology, 2009 | ||
10 | “Effect of oxygen migration and interface engineering on resistance switching behavior of reactive metal/polycrystalline Pr0.7Ca0.3MnO3 device for nonvolatile memory applications” | |
| Dong-jun Seong, Jubong Park, Nodo Lee, Musarrat Hasan, Seungjae Jung, Hyejung Choi, Joonmyoung Lee, Minseok Jo, Wootae Lee, Sangsu Park, Seonghyun Kim, Yun Hee Jang, Y. Lee, M. Sung, D. Kil, Y. Hwang, S. Chung, S. Hong, J. Roh, Hyunsang Hwang Proc. International Electron Devices Meeting (IEDM), 2009 | ||
| “Highly scalable Z-RAM with remarkably long data retention for DRAM application” | |
| Tae-Su Jang, Joong-Sik Kim, Sang-Min Hwang, Young-Hoon Oh, Kwang-Myung Rho, Seoung-Ju Chung, Su-Ock Chung, Jae-Geun Oh, S. Bhardwaj, Jungtae Kwon, D. Kim, M. Nagoga, Yong-Taik Kim, Seon-Yong Cha, Seung-Chan Moon, Sung-Woong Chung, Sung-Joo Hong, Sung-Wook Park Digest of Technical Papers - Symposium on VLSI Technology, 2009 | |
11 | |
| “Effect of oxygen migration and interface engineering on resistance switching behavior of reactive metal/polycrystalline Pr0.7Ca0.3MnO3 device for nonvolatile memory applications” | |
| Dong-jun Seong, Jubong Park, Nodo Lee, Musarrat Hasan, Seungjae Jung, Hyejung Choi, Joonmyoung Lee, Minseok Jo, Wootae Lee, Sangsu Park, Seonghyun Kim, Yun Hee Jang, Y. Lee, M. Sung, D. Kil, Y. Hwang, S. Chung, S. Hong, J. Roh, Hyunsang Hwang Proc. International Electron Devices Meeting (IEDM), 2009 | |
10 | |
2008
9 | “Research on switching property of an oxide/copper sulfide hybrid memory” | |
| Jaeyun Yi, Sung-Woo Kim, Yoshio Nishi, Yun-Taek Hwang, Sung-Woong Chung, Sung-Joo Hong, Sung-Wook Park Jae-Goan Jeong, Sung-Joo Hong, Sung-Wook Park, In-Young Chung, Y.J. Park, Hong Shick Min Non-volatile memory technology (NVMT), 2008 | ||
8 | “Fully integrated and functioned 44nm DRAM technology for 1GB DRAM” | |
| Hyunjin Lee, Dae-Young Kim, Bong-Ho Choi, Gyu-Seong Cho, Sung-Woong Chung, Wan-Soo Kim, Myoung-Sik Chang, Young-Sik Kim, Junki Kim, Tae-Kyun Kim, Hyung-Hwan Kim, Hae-Jung Lee, Han-Sang Song, Sung-Kye Park, Jin-Woong Kim, Sung-Joo Hong, Sung-Wook Park Jae-Goan Jeong, Sung-Joo Hong, Sung-Wook Park, In-Young Chung, Y.J. Park, Hong Shick Min Digest of Technical Papers - Symposium on VLSI Technology, 2008 | ||
| “Research on switching property of an oxide/copper sulfide hybrid memory” | |
| Jaeyun Yi, Sung-Woo Kim, Yoshio Nishi, Yun-Taek Hwang, Sung-Woong Chung, Sung-Joo Hong, Sung-Wook Park Non-volatile memory technology (NVMT), 2008 | |
9 | |
| “Fully integrated and functioned 44nm DRAM technology for 1GB DRAM” | |
| Hyunjin Lee, Dae-Young Kim, Bong-Ho Choi, Gyu-Seong Cho, Sung-Woong Chung, Wan-Soo Kim, Myoung-Sik Chang, Young-Sik Kim, Junki Kim, Tae-Kyun Kim, Hyung-Hwan Kim, Hae-Jung Lee, Han-Sang Song, Sung-Kye Park, Jin-Woong Kim, Sung-Joo Hong, Sung-Wook Park Digest of Technical Papers - Symposium on VLSI Technology, 2008 | |
8 | |
2007
7 | “Analysis of Bridge Failure between PPG and LPP in Fin Cell Transistor” | |
| Jungho Lee, Sung-Woong Chung, Seung Pyo Park, Myung Sick Chang, Jung Hoon Lee, Sung-Joo Hong Conference ISTFA, 2007 p345 | ||
6 | “Reliability Studies on Non Planar DRAM Cell Transistor” | |
| Myoung Jin Lee, Seonghoon Jin, Chang-Ki Baek, Sung-Min Hong, Soo-Young Park, Hong-Hyun Park, Sang-Don Lee, Sung-Woong Chung, Jae-Goan Jeong, Sung-Joo Hong, Sung-Wook Park, In-Young Chung, Y.J. Park, Hong Shick Min Intrenational Reliability physics symposium, 2007 | ||
| “Analysis of Bridge Failure between PPG and LPP in Fin Cell Transistor” | |
| Jungho Lee, Sung-Woong Chung, Seung Pyo Park, Myung Sick Chang, Jung Hoon Lee, Sung-Joo Hong Conference ISTFA, 2007 p345 | |
7 | |
| “Reliability Studies on Non Planar DRAM Cell Transistor” | |
| Myoung Jin Lee, Seonghoon Jin, Chang-Ki Baek, Sung-Min Hong, Soo-Young Park, Hong-Hyun Park, Sang-Don Lee, Sung-Woong Chung, Jae-Goan Jeong, Sung-Joo Hong, Sung-Wook Park, In-Young Chung, Y.J. Park, Hong Shick Min Intrenational Reliability physics symposium, 2007 | |
6 | |
2006
5 | “Highly Scalable Saddle-Fin(S-Fin) transistor for sub-50nm DRAM technology” | |
| Sung-Woong Chung, Sang-Don Lee, Se-Aug Jang, Min-Soo Yoo, Kwang-Ok Kim, Chai-O Chung, Sung Yoon Cho, Heung-Jae Cho, Lae-Hee Lee, Sun-Hwan Hwang, Jin-Soo Kim, Bong-Hoon Lee, Hyo Geun Yoon, Hyung-Soon Park, Seung-Joo Baek, Yun-Seok Cho, Noh-Jung Kwak, Hyunchul Sohn, Seung-Chan Moon, Kyung-Dong Yoo, Jae-Goan Jeong, Jin-Woong Kim, Sung-Joo Hong, Sung-Wook Park Digest of Technical Papers - Symposium on VLSI Technology, 2006 | ||
| “Highly Scalable Saddle-Fin(S-Fin) transistor for sub-50nm DRAM technology” | |
| Sung-Woong Chung, Sang-Don Lee, Se-Aug Jang, Min-Soo Yoo, Kwang-Ok Kim, Chai-O Chung, Sung Yoon Cho, Heung-Jae Cho, Lae-Hee Lee, Sun-Hwan Hwang, Jin-Soo Kim, Bong-Hoon Lee, Hyo Geun Yoon, Hyung-Soon Park, Seung-Joo Baek, Yun-Seok Cho, Noh-Jung Kwak, Hyunchul Sohn, Seung-Chan Moon, Kyung-Dong Yoo, Jae-Goan Jeong, Jin-Woong Kim, Sung-Joo Hong, Sung-Wook Park Digest of Technical Papers - Symposium on VLSI Technology, 2006 | |
5 | |
2002
4 | “Novel shallow trench isolation process using flowable oxide CVD for sub-100 nm DRAM” | |
| Sung-Woong Chung, Sang-Tae Ahn, Hyunchul Sohn, Jachun Ku, Sungki Park, Yong-Wook Song, Hyo-Sik Park, Sang-Don Lee Proc. International Electron Devices Meeting (IEDM), 8-11, pp.233-236, 2002 | ||
| “Novel shallow trench isolation process using flowable oxide CVD for sub-100 nm DRAM” | |
| Sung-Woong Chung, Sang-Tae Ahn, Hyunchul Sohn, Jachun Ku, Sungki Park, Yong-Wook Song, Hyo-Sik Park, Sang-Don Lee Proc. International Electron Devices Meeting (IEDM), 8-11, pp.233-236, 2002 | |
4 | |
Before 1999
3 | “Shallow Trench Isolation Characteristics with High-Density-Plasma (HDP) CVD Gap-Fill Oxide for Deep-Submicron CMOS Technologies” | |
| Seungho Lee, Kuchul Jung, Jeonghwan Son, Sungwoong Chung, Minchul Chae, Junyong Kim, Wouns Yang, Youngiong Lee, Jeongmo Hwang International Conference on Solid State Devices and Materials, IIanlamatsu,1997, pp.524-525 | ||
2 | “Optimization of repeater size to minimize interconnect line-induced delay time for high performance VLSI circuits” | |
| Myoung-Jun Jang;Hi-Deok Lee;Myoung-Kyu Park;Hae-Wang Lee;Kyung-Jin Yoo;Sang-Bok Lee;Sung-Woong Chung;Dae-Gwan Kang;Jeong-Mo Hwang ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361), 1999 | ||
1 | “Integration of Intermetal Dielectrics using Hydrogen Silsesquioxane Spin-On-Glass for sub-Quarter Micron 5 level interconnect Systems.” | |
| Sung-Woong Chung, Jin Woong Kim, Dae-Won Suh, Nae-Hak Park, Jin-Won Park, Jae-Jeong Kim Proc. Dielectrics for ULSI Multilevel interconnection conference (DUMIC) 1998, 151-154 | ||
| “Shallow Trench Isolation Characteristics with High-Density-Plasma (HDP) CVD Gap-Fill Oxide for Deep-Submicron CMOS Technologies” | |
| Seungho Lee, Kuchul Jung, Jeonghwan Son, Sungwoong Chung, Minchul Chae, Junyong Kim, Wouns Yang, Youngiong Lee, Jeongmo Hwang International Conference on Solid State Devices and Materials, IIanlamatsu,1997, pp.524-525 | |
3 | |
| “Optimization of repeater size to minimize interconnect line-induced delay time for high performance VLSI circuits” | |
| Myoung-Jun Jang;Hi-Deok Lee;Myoung-Kyu Park;Hae-Wang Lee;Kyung-Jin Yoo;Sang-Bok Lee;Sung-Woong Chung;Dae-Gwan Kang;Jeong-Mo Hwang ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361), 1999 | |
2 | |
| “Integration of Intermetal Dielectrics using Hydrogen Silsesquioxane Spin-On-Glass for sub-Quarter Micron 5 level interconnect Systems.” | |
| Sung-Woong Chung, Jin Woong Kim, Dae-Won Suh, Nae-Hak Park, Jin-Won Park, Jae-Jeong Kim Proc. Dielectrics for ULSI Multilevel interconnection conference (DUMIC) 1998, 151-154 | |
1 | |
419-1 C5, 80, Jigok-ro, Nam-gu, Pohang-si,
Gyeongsangbuk-do, Republic of Korea [37666]
swchung@postech.ac.kr
©2023 INNOVATIVE MEMORY PROCESS AND DEVICE. ALL RIGHTS RESERVED.
419-1 C5, 80, Jigok-ro, Nam-gu, Pohang-si, Gyeongsangbuk-do, Republic of Korea [37666]
©2023 INNOVATIVE MEMORY PROCESS AND DEVICE. ALL RIGHTS RESERVED.
